The present invention relates to a differential output circuit and a semiconductor device, and for example, to bias supply technology of transistors in a differential output circuit and a semiconductor device.
There is a rising demand for increasing the speed of data transmission between LSI internal circuits, between LSIs, between printed circuit boards, or between devices forming an electronic apparatus. In order to meet such a demand, output circuits which output differential signals in data transmission use low voltage transistors to realize a higher speed and lower power consumption. Although low voltage transistors operate at high speed, they have low durability against an excess voltage applied on elements.
Therefore, Japanese Patent No. 3764158 (Patent Document 1), for example, discloses an output circuit having a differential pair having a first transistor and a second transistor which respectively receive a first input voltage and a second input voltage; a first cascode transistor cascode-coupled to the first transistor; a second cascode transistor cascode-coupled to the second transistor; a first resistor component coupled to a ground line; and a second resistor component coupled to a power supply line, a gate of the first cascode transistor and a gate of the second cascode transistor being coupled to each other, each of the gates having supplied thereto a bias of an potential determined by dividing the resistive voltage between the first resistor component and the second resistor component, the first transistor outputting a first output signal via the first cascode transistor, the second transistor outputting a second output signal via the second cascode transistor. According to such an output circuit, it becomes possible to prevent destruction of a low voltage transistor in a data output circuit using low voltage transistors, even when excess voltage is applied to the circuit during circuit operation.
In addition, Japanese Patent Laid-Open No. 2010-283499 (Patent Document 2) also discloses a driver circuit similarly to Patent Document 1.
Furthermore, Japanese Patent Laid-Open No. 2009-171403 (Patent Document 3) discloses a differential transmitter which outputs a differential signal via a pair of differential signal lines, the differential transmitter having an input differential pair including a first and a second transistor coupled in common at one end respectively thereof and operating with a load of a termination resistor at a side of a receiving unit coupled via the differential signal line; a tail current supplying a constant current to the input differential pair; and an impedance regulation unit provided between the input differential pair and the differential signal lines to regulate load impedance of the first and the second transistor.